The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include sequential deposition of conductive and insulative layers on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove material from one or more conducting layers from the areas not covered by the mask, thereby etching the conducting layer or layers in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. Additional techniques, such as dual damascene processes, are used to form conductive vias which establish electrical contact between vertically-spaced conductive lines or layers in the circuits. The finished semiconductor product includes microelectronic devices including transistors, capacitors and resistors that form the integrated circuits on each of multiple die on a single wafer.
In the semiconductor industry, CMOS (complementary metal-oxide semiconductor) technology is extensively used in the fabrication of IC devices. CMOS technology typically involves the use of overlying layers of semiconductor material with the bottom layer being a dielectric layer and the top layer being a layer of doped silicon material that serves as a low-resistivity electrical contact gate electrode. The gate electrode, also referred to as a gate stack, typically overlies the dielectric layer.
In the semiconductor fabrication industry, silicon oxide (SiO2) is frequently used for its insulating properties as a gate oxide or dielectric. As the dimensions of device circuits on substrates become increasingly smaller, the gate dielectric thickness must decrease proportionately in field effect transistors (FETs) to approximately 3 to 3.5 nonometers. Accordingly, device performance and reliability can be adversely affected by such factors as interfacial defects, defect precursors and diffusion of dopants through gate dielectrics, as well as unintended variations in thickness in the gate oxide layer among central and peripheral regions of the layer.
Two types of CMOS device structures which are commonly fabricated in semiconductor technology include the MOSCAP (metal oxide semiconductor capacitor) structure and the MOSFET (metal oxide semiconductor field effect transistor) structure. Both of these structures include a substrate on which is deposited a dielectric layer having a high dielectric constant (k), such as a pad oxide layer. A silicon-containing gate, or gate stack, is deposited on the dielectric layer and connects a pair of trench oxide layers (in the case of a MOSCAP structure) or source and drain regions (in the case of a MOSFET structure).
FIG. 1 is a cross-section of an example of a polysilicon gate 20 formed between a source 16 and a drain 18 of a device 30 on a semiconductor wafer substrate 10. An STI (shallow trench isolation) structure 32 includes a shallow trench 12 filled with trench oxide 14 and separates devices from each other on the wafer substrate 10. A polysilicon silicide, or polycide 22, typically composed of nickel or cobalt, is deposited on the polysilicon gate 20, and an insulating layer 28 is deposited on the polycide 22. A source silicide 24 is deposited on the source 16, and a drain silicide 26 is deposited on the drain 18.
As shown in FIG. 2, an STI structure 36 is fabricated by initially depositing a pad oxide layer 42 on a silicon substrate 40 and a silicon nitride layer 44 on the pad oxide layer 42. One or more trenches 38 is etched through the silicon nitride layer 44 and the pad oxide layer 42, into the substrate 40. A liner oxide layer 46 is then deposited on the sidewalls and bottom of the trench or trenches 38. After a liner densification step, each trench 38 is filled with a trench oxide 48, followed by chemical mechanical planarization of the oxide layer 50 above the trench oxides 48. During the CMP step, the silicon nitride layer 44 serves as a polish-stop material to prevent over-polishing of the STI structure 36.
In a subsequent silicon nitride etching step, the silicon nitride layer 44 is then etched or stripped from the underlying pad oxide layer 42. This is accomplished typically by dipping the wafer substrate 40 into a wet bench tank that contains hot phosphoric acid (H3PO4). In a subsequent pad oxide etching step, the pad oxide layer 42 is etched to a desired target thickness.
The silicon nitride etching step and the pad oxide etching step are typically both carried out in the same wet bench tank that contains hot phosphoric acid. During the silicon nitride etching step, silicon oxide (SiO) is generated as a reaction by-product and accumulates in the wet bench tank. Accordingly, as a lot of successive wafers is processed, the quantity of silicon oxide which accumulates in the tank increases with the run number of the lot. The level of silicon oxide in the tank eventually reaches a saturation point (120 ppm).
One of the problems associated with the conventional method of etching the silicon nitride layer and the pad oxide layer in the same wet bench etch tank is that the etch rate for the pad oxide layer is indirectly proportional to the quantity or concentration of silicon oxide precipitates in the tank. Because the quantity of silicon oxide in the tank increases as the process run number increases, the pad oxide layer for wafers in the higher run number range cannot be etched to within the desired target thickness. Thus, the number of runs in a processing sequence must normally be restricted in order to attain precise control of the pad oxide layer thickness.
Placing a restriction on the number of runs in a processing sequence, however, has limitations, since the variation in pad oxide layer thickness among wafers in such a sequence can vary by as much as 40 angstroms (typically about 70˜110 angstroms). Furthermore, the silicon oxide precipitates form quickly in the processing tank and have a tendency to become attached to the wafer surface. This induces surface defects in the devices being fabricated on the wafers. Accordingly, a novel method is needed for the etching of a silicon nitride layer from a pad oxide layer and etching of the pad oxide layer to a desired target thickness, such as during the fabrication of STI structures on semiconductor wafers, while eliminating or substantially reducing the formation of silicon oxide precipitates in the oxide-etching medium.
An object of the present invention is to provide a novel method for etching an oxide layer to a selected target thickness.
Another object of the present invention is to provide a novel method for stripping a silicon nitride layer from a pad oxide layer and etching the pad oxide layer to a selected target thickness.
Yet another object of the present invention is to provide a novel method in which a silicon nitride layer is stripped from a pad oxide layer and the pad oxide layer is etched to a selected target thickness in separate processing tanks.
Still another object of the present invention is to provide a novel method which is capable of achieving a thickness for a pad oxide layer to within about 5 angstroms of a target thickness for the layer.
Yet another object of the present invention is to provide a novel method which prevents or substantially reduces the accumulation of silicon oxide precipitates in a processing tank in which the etching of a pad oxide layer to a selected target thickness is carried out.
A still further object of the present invention is to provide a novel dual-tank etch method which is suitable for any process in which it is necessary to strip a silicon nitride layer from a pad oxide layer and etch the pad oxide layer to a selected target thickness, including but not limited to the fabrication of shallow trench isolation (STI) structures.
Another object of the present invention is to provide a novel dual-tank etch method which eliminates or substantially reduces the formation of defects on wafers caused by silicon oxide precipitates in an etchant medium.